The table below shows the patents by Flynn and Jaggar. Note: Some patents may have other joint inventors.
| Patent Number | Author | Title |
|---|---|---|
| 5,506,976 | DJ | Branch cache |
| 5,525,971 | DF | Integrated circuit |
| 5,568,646 | DJ | Multiple instruction set mapping |
| 5,583,804 | DJ | Data processing using multiply-accumulate instructions |
| 5,642,479 | DF | Trace analysis of data processing |
| 5,642,487 | DF | Integrated circuit and method of operation |
| 5,680,599 | DJ | Program counter save on reset system and method |
| 5,680,643 | DF | Data bus including address request line for allowing request for a subsequent address word during a burst mode transfer |
| 5,701,493 | DJ | Exception handling method and apparatus in data processing systems |
| 5,737,625 | DJ | Selectable processing registers and method |
| 5,740,461 | DJ | Data processing with multiple instruction sets |
| 5,748,515 | DJ | Data processing condition code flags |
| 5,748,518 | DJ | Data processing divider |
| 5,749,094 | DJ | Invalid write recovery apparatus and method within cache memory |
| 5,764,173 | DF | Digital to analogue converter having input control bits for selecting a pulse width modulated output signal |
| 5,774,083 | DF | Digital to analogue converter comprising a converting circuit and a reference circuit both being formed in a single integrated circuit |
| 5,784,602 | DJ | Method and apparatus for digital signal processing for integrated circuit architecture |
| 5,828,852 | DF | Method for operation of a bus system for highly flexible and quick data transmission between units connected to the bus system and configuration for carrying out the method |
| 5,881,257 | DJ | Data processing system register control |
| 5,881,259 | DJ | Input operand size and hi/low word selection control in data processing systems |
| 5,961,633 | DJ | Execution of data processing instructions |
| 5,969,975 | DJ | Data processing apparatus registers |
| 6,034,545 | DF | Macrocell for data processing circuit |
| 6,069,611 | DF | Display palette programming utilizing frames of data which also contain color palette updating data to prevent display distortion or sparkle |
| 6,115,729 | DJ | Floating point multiply-accumulate unit |
| 6,148,314 | DJ | Round increment in an adder circuit |
| 6,189,094 | DJ | Recirculating register file |
| 6,216,222 | DJ | Handling exceptions in a pipelined data processing apparatus |
| 6,247,113 | DJ | Coprocessor opcode division by data type |
| 6,282,634 | DJ | Apparatus and method for processing data having a mixed vector/scalar register file |
| 6,321,329 | DJ | Executing debug instructions |
| 6,343,358 | DJ | Executing multiple debug instructions |
| 6,345,335 | DF | Data processing memory system |
| 6,360,189 | DJ | Data processing apparatus and method for performing multiply-accumulate operations |
| 6,415,365 | DF | Write buffer for use in a data processing apparatus |
| 6,446,221 | DJ | Debug mechanism for data processing systems |
| 6,542,916 | DJ | Data processing apparatus and method for applying floating-point operations to first… |
| 6,883,102 | DF | Apparatus and method for performing power management functions |
| 6,950,951 | DF | Power control signalling |
| 7,017,030 | DJ | Prediction of instructions in a data processing apparatus |
| 7,154,317 | DF | Latch circuit including a data retention latch |
| 7,181,633 | DF | Data processing performance control based on a status signal indicating the maximum voltage that can be supported |
| 7,194,647 | DF | Data processing performance control |
| 7,206,982 | DF | Diagnostic mechanism for an integrated circuit |
| 7,240,144 | DF | Arbitration of data transfer requests |
| 7,283,930 | DF | Data processing performance control |
| 7,315,796 | DF | Data processing performance control |
| 7,321,942 | DF | Performance counter for adding variable work increment value that is dependent upon clock frequency |
| 7,600,141 | DF | Data processing performance control |
| 7,605,644 | DF | Integrated circuit power-on control and programmable comparator |
| 7,737,720 | DF | Virtual power rail modulation within an integrated circuit |
| 7,808,273 | DF | Reducing leakage power in low power mode |
| 7,822,955 | DF | Data processing apparatus and method for utilizing endianess independent data values |
| 7,863,778 | DF | Power controlling integrated circuit cell |
| 7,898,278 | DF | Power control circuitry, circuitry for analysing a switched power rail, and method of controlling connection of a power source to a switched power rail |
| 7,977,822 | DF | Dynamically changing control of sequenced power gating |
| 8,330,478 | DF | Operating parameter monitoring circuit and method |
| 8,352,819 | DF | State retention using a variable retention voltage |
| 8,390,328 | DF | Supplying a clock signal and a gated clock signal to synchronous elements |
| 8,395,440 | DF | Apparatus and method for controlling power gating in an integrated circuit |
| 8,451,026 | DF | Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells |
| 8,451,039 | DF | Apparatus for storing a data value in a retention mode |
| 8,456,223 | DF | Integrated circuit with power gating |
| 8,615,687 | DF | Data processing system and method for regulating a voltage supply to functional circuitry of the data processing system |
| 8,639,960 | DF | Verifying state integrity in state retention circuits |
| 8,648,654 | DF | Integrated circuit and method for generating a layout of such an integrated circuit |
| 8,665,009 | DF | Integrated circuit and method for controlling load on the output from on-chip voltage generation circuitry |
| 8,732,499 | DF | State retention circuit adapted to allow its state integrity to be verified |
| 8,868,962 | DF | Monitoring circuit and method |
| 8,922,247 | DF | Power controlling integrated circuit and retention switching circuit |
| 9,170,282 | DF | Controlling voltage generation and voltage comparison |
| 9,496,785 | DF | Controlling voltage generation and voltage comparison |
| 9,720,434 | DF | Power gating in an electronic device |
| 9,935,634 | DF | Communication between voltage domains |
| 9,940,993 | DF | Storage bitcell with isolation |
| 10,007,314 | DF | Power signal interface |
| 10,209,755 | DF | No-operation power state command |
| 10,299,219 | DF | Transmitter, a receiver, a data transfer system and a method of data transfer |
| 10,354,721 | DF | Storage bitcell |
| 10,394,732 | DF | Interface device for a data processing system |